In solid-state dynamic memory, such as dynamic random access memory (“DRAM”), information stored in the memory decays over a period of time. Therefore, before the information decays to such an extent that it is lost, the memory contents must be refreshed. Conventionally, for a DRAM array the refreshing proceeds sequentially through each word of the array, under control of a counter. Since external accesses to the array tend to contend with refreshing, it is conventional to include design features for the array which mitigate contention. For example, it is conventional for a DRAM array to be segmented into numerous memory banks and for refreshing to proceed in one bank concurrently with an external access in another. However, refreshing and external access can still contend if both attempt to operate on the same bank at the same time. Therefore there is a need for an improved method and apparatus for refreshing of DRAM arrays.